1. Field of the Invention
The present invention relates to a nonvolatile flash memory device, and more particularly, to a method of verifying programming of a nonvolatile flash memory device.
2. Description of the Related Art
Data can be programmed in and erased from flash memory devices using a tunneling phenomenon. Such flash memory devices are appropriate for use as auxiliary memory devices for mobile phones and other mobile devices, for example, due to high data retention, low power consumption, and strong durability with respect to external shocks. In NAND flash memory devices, in which a predetermined number of memory cells are connected in series, the size of a memory cell is smaller than the size of a memory cell of NOR flash memory devices, in which a predetermined number of memory cells are connected in parallel. Thus, NAND flash memory devices have a higher degree integration and are more useful as auxiliary memory devices with large capacity.
In NAND flash memory devices, multiple memory cells connected in series to one bitline constitute one string, and the string is divided into blocks having multiple pages based on memory cells connected to one wordline. In NAND flash memory devices having the above structure, a read operation and a program operation are performed in one page unit, and an erase operation is performed in one block unit.
FIG. 1 includes a circuit diagram and sectional diagrams for illustrating a conventional method of applying a voltage during a program operation of a NAND flash memory device. Referring to FIG. 1, a memory cell array 1 includes memory strings A0 and A1, each having memory cells connected to common wordlines WL0-WL31. A first memory string A0 is connected to a first bitline BL0, and a second memory string A1 is connected to a second bitline BL1. Memory cell transistors MT0A-MT31A, each having a floating gate, are connected in series to the first memory string A0. The drain of the memory cell transistor MT0A is connected to a first bitline BL0 through a string selection transistor SG1A connected to a string selection line SSL, and the source of the memory cell transistor MT31A is connected to a ground voltage VSS through a ground selection transistor SG2A connected to a ground selection line GSL. Memory cell transistors MT0B-MT31B, each having a floating gate, are connected to the second memory string A1 in series. The drain of the memory cell transistor MT0B is connected to a second bitline BL1 through a string selection transistor SG1B, and the source of the memory cell transistor MT31B is connected to the ground voltage VSS through a ground selection transistor SG2B.
FIG. 2 is a flow diagram illustrating a conventional method of verifying a programming operation. With reference to FIGS. 1 and 2, a programming operation is performed after an erase operation. For example, assuming that memory cell transistor MT13A of the first memory string A0 is selected for programming, 0V is applied to the first bitline BL0 to set up the bitline BL0 (210), and data to be programmed in the selected memory cell transistor MT13A is loaded into the bitline BL0. The string selection transistor SG1A is turned on so that the first memory string A0 is connected to the first bitline BL0, and the ground selection transistor SG2A is turned off. A program voltage Vpgm of approximately 14-20 V is applied to selected wordline WL13 (212), and a pass voltage Vpass of approximately 7-10 V is applied to unselected wordlines WL0-WL12 and WL14-WL31 (211), for example. Accordingly, in the memory cell transistor MT13A, electrons are tunneled to a floating gate from a channel, so that a threshold voltage increases to a positive value. After programming, the selected wordline WL13 and the unselected wordlines WL0-WL12 and WL14-WL31 are recovered, for example, to the ground voltage VSS (213, 214). The bitline BL0 is likewise recovered (215).
Since the program operation is performed in one page unit, when the program voltage Vpgm is applied to the selected wordline WL13 in FIG. 1, the same program voltage Vpgm is applied to the gate of the memory cell transistor MT13B that belongs to the second memory string A1, which is not selected. In other words, the memory cell MT13A to be programmed and the memory cell MT13B not to be programmed (hereinafter, referred to as “a program inhibit cell”) are connected to one wordline WL13 within one page, and the program voltage Vpgm is applied to the selected wordline WL13. Thus, the program inhibit cell MT13B may be soft programmed by the program voltage Vpgm. This is referred to as program disturbance.
In order to prevent program disturbance of the program inhibit cell MT13B, a power supply voltage VDD is applied to the second bitline BL1, and a channel voltage is increased using self-boosting due to capacitive coupling between the gate and the channel. As a result, a voltage difference between the gate of the program inhibit cell MT13B and the channel is sufficiently reduced so that electrons are not tunneled to the floating gate and program disturbance of the program inhibit cell MT13B is prevented.
Channel voltages of the first and second memory strings A0 and A1 depend on the pass voltage Vpass supplied to each of the unselected wordlines WL0-WL12 and WL14-WL31. As the pass voltage Vpass increases, a state where the program inhibit cell MT13B is soft programmed may be avoided. However, as the pass voltage Vpass increases to prevent program disturbance, the memory cells connected to each of the unselected wordlines WL0-WL12 and WL14-WL31 may be soft programmed by the pass voltage Vpass. This is referred to as pass disturbance. Thus, the pass voltage Vpass is determined in consideration of program disturbance and pass disturbance conditions, and has characteristics as shown in pass voltage window (W1) of FIG. 3, for example, indicating a number of failed bits as a function of increasing pass voltage Vpass.
Referring back to FIG. 2, after all of the memory cells are programmed, an operation of verifying whether corresponding memory cells are correctly programmed is performed. The verification operation includes a program recovery operation followed by a verification read operation. The program recovery operation includes discharging a bitline (220) and precharging the bitline (221) in order to set a bitline voltage to a predetermined value so as to read data. The verification read operation includes developing data of the bitline (222), sensing the data of the bitline (223) and verifying, reading and recovering the data of the bitline (224) in order to read and latch the data of the bitline.
When at least one of the memory cells is not sufficiently programmed (failed) (225), the program operation is repeatedly performed a predetermined number of times. The program voltage used in the next loop program operation is set higher than the program voltage used in the previous loop program operation. The selected memory cells may thus be re-programmed. Passing the memory cells results in mode recovery (230) and the program operation is complete (240).
FIG. 4 is a circuit diagram for illustrating a conventional method of applying a voltage, including the bitline data sensing operation (223) and the verification read recovery operation (224) of the verification read operation shown in FIG. 2. Referring to FIG. 4, in the bitline data sensing operation (223), for example, a read voltage Vread of approximately 4.5 V is applied to a string selection line SSL, wordlines WL0-WL31, and a ground selection line GSL so that data of the bitline BL is sensed. In the subsequent verification read recovery operation (224), the bitline BL is discharged to a ground voltage 0V.
If a memory cell MT13A to be programmed is not sufficiently programmed, after the verification read recovery operation (224), during a next program loop operation, the pass voltage Vpass is applied to memory cells connected to each of the unselected wordlines WL0-WL12 and WL14-WL31. In this case, since channel voltages of the first and second memory strings A0 and A1 are boosted from the ground voltage 0V, the pass voltage Vpass must be increased.
Furthermore, due to large-capacity and high-speed applications, in order to achieve higher cell density in the same chip size, the size of a block, which is an erase operation unit of a NAND flash memory device, and the size of a page, which is a read and program operation unit, are increased. As page units increase in size, the pass voltage for avoiding a program disturbance in a memory cell increases. As such, a programming operation occurs in which a pass voltage window is reduced (W2<W1), as shown in FIG. 3.